A typical example of the the control system generating circuit incorporated in the semiconductor memory device is illustrated in FIG. 1 of the drawings. The control signal generating circuit illustrated in FIG. 1 largely comprises a plurality of flip-flop circuits 1, 2, 3, 4, 5 and 6 connected in cascade to form a shift register circuit 7, and each of the flip-flop circuits 1 to 6 has an input terminal 8, a clock terminal 9 and a pair of output terminals 10 and 11. The first flip-flop circuit 1 is electrically connected at the input terminal 8 to an inverter circuit 12 which is supplied with an external control signal EXT from the outside thereof, and the input terminals 8 of the second to final flip-flop circuits 2 to 6 are coupled to the output terminals 10 of the first to fifth flip-flop circuits 1 to 5, respectively. A clock signal CLK is directly supplied to the clock terminals 9 of the first, third and fifth flip-flop circuits 1, 3 and 5, but the remaining flip-flop circuits 2, 4 and 6 are supplied at the clock terminals CLK thereof with the inverse of the clock signal fed from an inverter circuit 13.
For production of a chip enable signal CE and a precharging signal PCH, the control signal generating circuit illustrated in FIG. 1 further comprises two-input AND gates 14 and 15. The AND gate 14 is connected at the two input terminals thereof to the output terminal 10 of the first flip-flop circuit 1 and the output terminal 11 of the final flip-flop circuit 6, respectively, and the two input terminals of the AND gate 15 are coupled in parallel to the output terminal 10 of the flip-flop circuit 2 and the output terminal 11 of the flip-flop circuit 5.
In operation, the AND gate 14 produces the chip enable signal CE rising to an active high voltage level synchronous with the active high voltage level appearing at the output terminal 10 of the first flip-flop circuit 1 and decaying synchronous with the active high voltage level at the output terminal 10 (or the inactive low voltage level at the output terminal 11) of the final flip-flop circuit 6. In a similar manner, the AND gate 15 produces the precharging signal PCH rising to an active high voltage level synchronous with the active high voltage level at the output terminal 10 of the second flip-flop circuit 2 and decaying in synchronous with the active high voltage level at the output terminal 10 of the flip-flop circuit 5. Each of the flip-flop circuits 1 to 6 is shifted between two stable output states in response to the clock signal CLK or the inverse thereof, so that the duration of each control signal is decided by the number N of the stages of flip-flop circuits between the two input terminals thereof to be N times longer than the width of each clock pulse CLK. Thus, the control signal generating circuit illustrated in FIG. 1 is operative to produce the control signals CE and PCH each having the duration which is N times longer than the width of each clock pulse CLK.
However, a problem in encountered in the prior-art control signal generating circuit in precise determination of the duration of the control signal. In detail, each control signal continues in the active level for a time period N times longer than the width of the clock pulse CLK as described above, so that a higher frequency clock signal is needed for production of timings close to each other. The higher frequency the clock signal has, the less reliability the control signal generator has in operation. Moreover, another difficulty is encountered in the prior-art control signal generating circuit in circuit design and in integration layout if a higher frequency clock signal is used. Then, another approach should be taken to produce the close timings for the control signals.